Zynq-7000 Extensible Processing Platform

Supported FPGA/CPLDs: 28nm based-product

The Zynq™-7000 family is the world’s first Extensible Processing Platform (EPP). This innovative class of product combines an industry-standard ARM® dualcore Cortex™-A9 MPCore™ processing system with Xilinx 28nm unified programmable logic architecture. This processor-centric architecture delivers a complete embedded processing platform that offers developers ASIC levels of performance and power consumption, the flexibility of an FPGA and the ease of programmability of a microprocessor.

The four devices of the Zynq-7000 EPP family allow designers to target cost sensitive as well as high- performance applications from a single platform using industry-standard tools. The tight integration of the processing system with programmable logic allows designers to build accelerators and peripherals to speed key functions by up to 10x. ARM architecture and ecosystem maximizes productivity and eases development for software and hardware developers.

Unlike ASICs and ASSPs, Zynq-7000 devices allow designers to modify their design throughout the development phase and after the system is in production. In addition, the Zynq-7000 EPP family, with over 3000 interconnections between its processing system and the programmable logic, offers levels of performance that two-chip solutions (ASSP+FPGA) cannot match due to limited IO bandwidth and limited power budgets.


  • Dual ARM Cortex-A9 MPCore
    • Up to 800MHz
    • Enhanced with NEON Extension and Single & Double Precision Floating point unit
    • 32kB Instruction & 32kB Data L1 Cache
  • Unified 512kB L2 Cache 256kB on-chip Memory
  • DDR3, DDR2 and LPDDR2 Dynamic Memory Controller
  • 2x QSPI, NAND Flash and NOR Flash Memory Controller


  • 2x USB2.0 (OTG), 2x GbE, 2x CAN2,0B 2x SD/SDIO, 2x UART, 2x SPI, 2x I2C, 4x 32b GPIO
  • AES & SHA 256b encryption engine for secure boot and secure configuration
  • Dual 12bit 1Msps Analog-to-Digital converter
    • Up to 17 Differential Inputs
  • Advanced Low Power 28nm Programmable Logic:
    • 28k to 350k Logic Cells (approximately 430k to 5.2M of equivalent ASIC Gates)
    • 240KB to 2180KB of Extensible Block RAM
    • 80 to 900 18×25 DSP Slices (58 to 1080 GMACS peak DSP performance)
  • PCI Express® Gen2x8 (in largest devices)
  • 154 to 404 User IOs (Multiplexed + SelectIO™)
  • 4 to 16 12.5Gbps Transceivers (in largest devices)


Automotive, Broadcast, Medical Imaging, Industrial Motor Control


Contact Information


2100 Logic Drive
San Jose, CA, 95124

tele: 408-559-7778

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