Synopsys, Inc.

Synplify Premier – Fast, Reliable FPGA Implementation and Debug

Supported FPGAs/CPLDs: All the major FPGA/CPLD families of devices from Achronix, Microsemi, Altera, Lattice Semiconductor, Silicon Blue and Xilinx are supported

As part of the Synopsys FPGA Design Solution, Synplify Premier software performs FPGA synthesis for programmable devices sold by Microsemi, Achronix, Altera, Lattice Semiconductor, SiliconBlue and Xilinx. The tool delivers the industry’s best Quality of Results (QoR), rapid runtimes using incremental synthesis, FAST synthesis mode and automated block-based design. Automatic compile-point technology automatically shortens synthesis runtimes by leveraging multi-core computers. Team-design features allow design team members to perform parallel and distributed development autonomously, further increasing efficiency. The Synplify Premier tool’s path-group technology makes design schedules more predictable by delivering results that are reproducible from one run to the next. The tool also delivers block-based RTL synthesis flows which fully integrate with 3rd party FPGA vendor block-based place and route design preservation flows, thereby shortening iteration runtimes, and preserving working, verified parts of the design from one run to the next.

For more information on Synplify Premier and other Synopsys FPGA implementation tools, visit us at


  • High reliability design for DO-254 compliance: Automatically implement safe FSMs and TMR insertion. Specify portions of the design to be preserved as debug logic or for deliberate redundancy purposes
  • Fast synthesis mode: Synthesize even the largest design in a fraction of the time required by other tools
  • DesignWare support: Easy ASIC code migration into an FPGA for prototyping. Integration with datapath and building block components in DesignWare IP
  • Automatic handling of DSP function: Infer DSP functions from RTL and map into vendor’s DSP hardware (e.g.: MACs, DSP48) for improved QoR
  • Team-design: Faster design iterations and design preservation. Develop a design in parallel and/or distributed environment using bottom-up or hybrid flow. No floorplanning required



  • Comprehensive language support including Verilog, VHDL, SystemVerilog and mixed-language
  • Supports Windows XP Pro and Windows 7 (32/64 bit)
  • Supports Linux, RHEL4, RHEL5, and SLES9 (32/64 bit)
  • Minimum hardware requirements: CPU 1 GHz speed or better, RAM 2Gb, HDD 300Mb free space


Synopsys’ Synplify Premier FPGA implementation software is available now. Request a free evaluation at


Aerospace/Defense, Automotive, Broadcast, Consumer, Data Processing and Storage, Industrial Automation, Medical Imaging, Wired Communcations, Wireless Communications


Contact Information

Synopsys, Inc.

700 E. Middlefield Road
Mountain View, CA, 94043

tele: 650.584.5000

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