Xilinx ISE Design Suite 13

Supported FPGA/CPLDs: Virtex Series, Kintex Series, Artix Series and Spartan Series and CoolRunner Family

ISE® Design Suite 13 maximizes productivity, by leveraging open industry standards to accelerate design creation, verification, implementation, and lower system power for design teams targeting Xilinx FPGAs. New to the award winning design tool and IP suite are enhancements which improve productivity across SoC design teams including the progression towards true plug-and-play IP.

Also new is an application called Documentation Navigator, allowing users to view and manage Xilinx design documentation (software, hardware, IP, and more) from one place, with easy-to-use download, search and notification features. To try out the new Documentation Navigator, now in open beta release, please visit www.xilinx.com/download today.


  • The new AMBA® 4 AXI-4 interconnect protocol IP enables design teams to easily customize their system topology for either performance or area resulting in optimal system bandwidth for interconnect and memory interfaces.
  • Accelerated Verification: – Leveraging Xilinx’s large portfolio of development boards, kits and Xilinx’s ISE Simulator new hardware Co-Simulation, verification engineers can test implemented blocks of the design while leaving blocks under development in the simulator accelerating overall verification by up to 100 times faster than native simulation.
  • Design Creation and Analysis – The PlanAhead™ Design and Analysis tool accelerates time to production with an integrated front-to-back environment with design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis, place and route. The end result is rapid convergence on power consumption, resource utilization, and performance with fewer time-consuming design iterations.


  • Team Design – The new team design methodology addresses the challenge of multiple engineers working on a single project by providing a methodology for groups of developers to work in parallel.
  • Enhanced Optimizations – Advanced optimizations, including intelligent clock gating that provides up to 30 percent dynamic power reduction, facilitates faster timing closure and timing preservation increasing overall productivity and reducing design iterations.


  • ISE Design Suite Logic Edition: Front-to-back FPGA Logic Design with complete flow for RTLbased design
  • ISE Design Suite DSP Edition: Complete design suite with DSP-specific IP and System Generator for rapid development of high performance DSP systems
  • ISE Design Suite Embedded Edition: Integrated Embedded Design Solution supporting both embedded HW and SW engineers
  • ISE Design Suite System Edition: Integrated tool and IP environment supporting the combined methodologies of logic/connectivity, embedded, and DSP design

Visit www.xilinx.com/ise to download a free 30-day evaluation, and to learn more.


Contact Information


2100 Logic Drive
San Jose, CA, 95124

tele: 408-559-7778

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