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  • FPGA Blog

    FPGA Blog

    Tokyo Electron Device Debuts TB-7Z-020-EMC Extension Microcontroller Card
    Published. December 5, 2012

    Tokyo Electron Device (TED) launched the TB-7Z-020-EMC extension microcontroller card. It features a Zynq-7000 All Programmable SoC. The TED TB-7Z-020-EMC features both an ARM Cortex-A9 MPcore with on-chip connection to a FPGA fabric and a Zynq-7000. It can be used to implement evaluation systems into various different development projects. The card will ship in early [...]...


  • Tech Deseign Forums Blog

    Tech Deseign Forums Blog

    IPSoC: Tabula aims for 22nm white-label parts
    Published. December 4, 2012

    Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.The post IPSoC: Tabula aims for 22nm white-label parts appeared first on Tech Design Forums....


  • Practical Chip Design

    Practical Chip Design

    Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
    Published. November 30, 2012

    Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!...


  • Anablog

    Anablog

    Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
    Published. November 30, 2012

    Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!...


  • Now Hear This!

    Now Hear This!

    Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
    Published. November 30, 2012

    Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!...


  • EDA Graffiti

    EDA Graffiti

    Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
    Published. November 30, 2012

    Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!...


  • Brian's Brain

    Brian's Brain

    Read BDTI’s Evaluation of Our Floating-Point DSP on Hardware
    Published. November 30, 2012

    Download this white paper to read a performance evaluation of Altera’s FPGA floating-point digital signal processing (DSP) design flow on 28 nm hardware by BDTI, an independent technology analysis firm. Also, watch a preview of the white paper today!...


  • Green Hills Software

    Green Hills Software

    Green Hills Software Joins Xilinx Alliance Program
    Published. October 31, 2012

    Industry-Leading Safety and Security Solutions for Zynq-7000 All Programmable SoC...


  • Electronics Design Articles

    Electronics Design Articles

    JESD204B Converters Simplify FPGA And ASIC Interfacing
    Published. November 20, 2012

    By Don TuiteJESD204B SERDES Tx and Rx facilitates connecting multiple high-speed, high-res data converters to FPGAs or ASICs. story describes how it does that with reduced pin-count and low, deterministic, latency....


  • Frank Schirrmeister Blog

    Frank Schirrmeister Blog

    Optimizing ARM Based Designs for Low Power using Emulation
    Published. November 19, 2012

    The month November goes to the Brits, no question. Not only did the James Bond movie Skyfall open, but Santa Clara also experienced somewhat of a "British Invasion" for ARM TechCon in the Santa Clara convention center. To be there properly I even brought out my favorite new pin striped suit ;). With that being at the cleaners now that ARM TechCon is over, I am reflecting on what I heard. In my mind ARM TechCon's focus was all about low-power -- at all levels of abstraction. Various...


  • Gabe On EDA

    Gabe On EDA

    Gray Cells In Your FPGA
    Published. November 15, 2012

    Shakeel Jeeawoody, VP of Marketing at Blue Pearl Software, published a paper that describes a technique developed by his company to significantly improve the inter block analysis for complex designs. The technique is called Grey Cell Methodology. read more...


  • Jason Andrews Blog

    Jason Andrews Blog

    Creating Custom File Systems and the Linux Loop Device
    Published. November 5, 2012

    A few weeks ago we had a crisis at our house. My son managed to delete the data from my daughter's USB memory stick. Not only did he delete it, but he did it in such a strange way I have no idea what he could have done. She was not too happy since all of her recent school work was on the memory stick. My best guess is that he deleted it by mistake, recognized what he had done, went into the recycle bin, but instead of restoring the files, tried to manually copy the files back to the stick...


  • Chris A. Ciufo on All Things Embedded

    Chris A. Ciufo on All Things Embedded

    “MicroFlix”…Funny name; how crazy would it be if Netflix joined the Microsoft Family?
    Published. October 29, 2012

    If Microsoft were to buy Netflix - and it's a big "if", since it's only a rumor - MSFT could join Apple, Amazon and Google in having a huge influence on the embedded industry. Continue reading →...


  • NextGenLog

    NextGenLog

    #MATERIALS: "2.5-D Chip to Precede Full 3-D"
    Published. September 14, 2012

    Integration of full 3-D semiconductors into the global market will take a back seat to silicon interposers, often called 2.5-D, which will grow to become a $1.6 billion market by 2017, according to Yole Development: R. Colin JohnsonHere is what Yole says about 3D silicon: After meeting with swift commercial success on a few initial applications, including MEMS, sensors and power amplifiers, 3D integration has been on everyone’s mind for the past five years. However, once the initial euphoria faded,...


  • EDA Blog

    EDA Blog

    Avnet Announces CC3000-Pmod Compatible Wi-Fi Adapter Development Kit
    Published. August 30, 2012

    Avnet Electronics Marketing Americas announced the CC3000-Pmod Compatible Wi-Fi Adapter. The Pmod compatible CC3000-based Wi-Fi adapter development kit features a built-in internet protocol stack. It is designed to attach to Avnet FPGA development boards and other host boards with a Pmod interface connector. The fully integrated and pre-certified Wi-Fi adapter is priced at $59. Read [...]...


  • Conversation Central

    Conversation Central

    Meeting the Challenges in Engineering Education
    Published. August 16, 2012

    Guest: Patrick Lysaght, Sr. Director, Xilinx Research Labs and University Program Host: Karen Bartleson, Sr. Director, Community Marketing, Synopsys Inc. and Rich Goldman, Vice President, Corporate Marketing and Strategic Alliances, Synopsys, Inc. If your browser doesn’t support Flash, click here to download the show and play it locally. There are great changes and great opportunities [...]...


  • TI E2E Community

    TI E2E Community

    Blog Post: Monthly Roundup: June
    Published. July 26, 2012

    Here are the top TI signal chain links in media coverage, awards and technical articles for the month of June. There is a nice mix of technical information spanning the signal chain to help you with your project – enjoy!    Analog  “Analog: back to the future, part one,” EDN Magazine, June 5, 2012. (Media Coverage)   Amplifiers  "Enhanced Low Dose Rate Sensitivity (ELDRS)," June 18, 2012. (Application Note) "LMP2012QML SET Radiation...


  • Team Specman Blog

    Team Specman Blog

    Achieve the Next Level of Verification Productivity with Specman Advanced Option
    Published. January 18, 2011

    Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely complex and, as a result, verifying every feature, in every mode of operation, under all conditions is extremely difficult to achieve.  Achieving high DUT coverage is getting very challenging....


  • Jack Erickson's Blog

    Jack Erickson's Blog

    C-to-Silicon Japan User Group and Ikegami Production Experience
    Published. July 3, 2012

    We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, information, and ideas so that we can all benefit. We have held these user groups so far this year in Israel, Japan, and internally to a large customer. To give an idea as to what is typically covered, we can look to Japan which hosted the most recent one.The...


  • Ran Avinun's Blog

    Ran Avinun's Blog

    Why the Demand for Acceleration and Emulation is Growing
    Published. February 14, 2011

    The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010), we introduced the Verification Computing Platform, enabling emulation, acceleration, and simulation all on one single platform. Customers who are designing SoCs at 40nm and below find this product necessary to meet the time-to-market and quality targets....


  • Steven Brown's Blog

    Steven Brown's Blog

    Virtual Flash Memory Gets Real
    Published. August 8, 2011

    This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging, and an increasing portion of the capability is delivered as firmware. Virtual prototypes of hardware for memory controllers, and the systems within which they operate, enable software to be developed months ahead of...


  • Team ESL Blog

    Team ESL Blog

    More Details on Post Silicon Embedded Software Verification With ISX
    Published. August 18, 2009

    Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in Germany, to the TeamESL blog for the next installment on post-silicon embedded software verification with ISX. This post is a discussion featuring Markus and Joerg talking to Malte Henzelmann and Ernst Zwingenberger of El Camino GmbH. It builds on the introduction that was provided in June titled OVM Metric Driven Verification with an FPGA-based Design. You guys built a cool demo connecting ISX to a FPGA...


  • Stephane Boucher's DSP Blog

    Stephane Boucher's DSP Blog

    New Discussion Group: DSP & FPGA
    Published. September 11, 2007

    I have just created a new discussion group for engineers implementing DSP functions on FPGAs. The creation of this group has been on my todo list for a long time. If you want to join the group, send a blank email to: fpgadsp-subscribe@yahoogroups.comAs usual, it should take a few weeks before there are enough members for interesting discussions to get started. ... read more...


  • Analog Insights

    Analog Insights

    HSPICE SIG event summary – Interview with our speakers – Overall impression and HSPICE latest features
    Published. February 28, 2012

    yes, an other field trip report   You may remember we held our HSPICE Special Interest Group event during DesignCon week. This event gives you an opportunity to talk with Synopsys HSPICE R&D personnel and hear what our customers have to say about using HSPICE in today’s most challenging designs. The agenda was: Altera: “28nm [...]...


  • To USB or not to USB

    To USB or not to USB

    The World’s First Demonstration of SuperSpeed InterChip (SSIC)
    Published. April 11, 2012

    Synopsys worked with the USB-IF SSIC Working Group to develop a SSIC Proof of Concept demonstration.  The USB-IF has been working on SSIC for some time.   This Proof of Concept in FPGA is to test the SSIC specification version 0.90 to see if it actually works in hardware. It worked (mostly).   We learned, [...]...


  • Verification Horizons Blog

    Verification Horizons Blog

    Get on the Fast Track to Advanced Verification with UVM Express
    Published. February 25, 2012

    Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the smallest FPGAs to the largest SoCs today. Still many design and verification teams that need to and are willing to embrace these technologies have yet to do so. Verification environments written with basic hardware description [...]...


  • Electronics Engineering Video Blog Podcast

    Electronics Engineering Video Blog Podcast

    EEVblog #193 – FPGA Implementation Tutorial
    Published. August 7, 2011

    Dave recently implemented an Actel Ignoo Nano and Xilinx Spartan 3 FPGA into a design, so decided to share some rather random notes on how to implement the FPGA’s in this scenario. From datasheet specs, traps for young players, global clocks, FPGA fabrics, core power supplies and decoupling, getting the schematic basics, JTAG and flash [...]...





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