IBM PowerPC 476FP Embedded Proccessor Core

A high-performance processor core with coherency-enabled level 1 caches


  • Superscalar, 5-issue, 32-bit RISC processor core
  • Implements Power Instruction Set Architecture (ISA), version 2.05; compliant with the Book III-E embedded operating environment
  • Integrated floating-point unit
  • Memory management optimized for multitasking embedded environments and symmetric multiprocessor (SMP) systems
  • L1 caches that support cache coherency in SMP systems
  • Tightly coupled to an L2 cache controller that supports coherency management
  • Extensive embedded debug facilities
  • Power-optimized functional and logical design

Execution pipelines

  • Five integer pipelines:
    • Branch
    • Multiply/divide
    • Complex integer
    • Simple integer
    • Load/store
  • Nine-stage, 5-issue, out-of-order issue and execution, and inorder completion
  • Up to 32 instructions in flight
  • Accelerated integer multiply and multiply-accumulate instructions
  • High-performance, out-of-order auxiliary processor pipeline interface that supports the floating-point unit
  • Shadow general purpose registers to reduce execution stalling and simplify operand forwarding
  • Little-endian memory support
  • SMP coherency support for load-with-reservation, store conditional
  • Speculative prefetching to the instruction cache
  • Dynamic branch prediction with a branch history table and link stack

Floating-point pipelines

  • Two floating-point pipelines:
    • Floating-point arithmetic
    • Floating-point load/store
  • ANSI/IEEE 754-1985 standard and Power ISA version 2.05 floating-point instructions supported:
    • Double precision
    • Single precision
  • Six-stage floating-point arithmetic execution pipeline

Memory management

  • Variable page sizes: 4 KB–1 GB
  • Software-managed translation lookaside buffer (TLB) entries
  • 1024-entry unified TLB; 4-way associative; hashed entry distribution
  • Separate data and instruction 8-entry shadow TLBs
  • 42-bit real address space; 49-bit virtual addressing support
  • 16-bit process ID
  • TLB cross-invalidate for SMP coherency support
  • Protected entries to optimize SMP paging management

Instruction and data caches

  • 32 KB, 4-way set-associative
  • 32-byte cache line
  • Pipelined 2-stage cache access
  • Nonblocking cache design
  • Cache-line locking capability, nonpersistent
  • Coherency snoop support for both caches
  • Parity protection


  • 64-bit time base
  • Decrementer with auto-load
  • Fixed interval timer
  • Watchdog timer with critical interrupt or reset

Debug facilities

  • Hardware execution debug facilities integrated in IEEE 1149.1 JTAG
  • Multiple instruction and data address breakpoints with multiple ranges
  • Data value comparison
  • Single-step, branch, trap and other debug events

Core interfaces

  • L2 cache system interfaces for instruction-side and data-side L1 caches
  • Snoop interface for TLB invalidate and reservation snooping
  • Device control register bus
  • Interrupt interface
  • JTAG and instruction trace ports for hardware debugging


PowerPC 476FP block diagram

Power control features

  • Functional idle mode
  • Global clock control
  • Automatic gating off of idle functional units
  • SRAM partition control gating
  • Extensive clock gating at latchand register level

Companion cores

  • L2 cache controller that supports memory coherency
  • Processor local bus controller that supports coherent and noncoherent functional blocks
  • DDR3 memory controller with coherency support
  • Multiprocessor interrupt controller

Target applications

  • Aerospace and defense applications
  • Digital TVs
  • Highly parallel, high-performance computers
  • Industrial controllers
  • I/O controllers and service processors
  • Network communications control planes
  • Printers and imaging
  • Storage systems and redundant array of independent disks (RAID) controllers

Application enablement

  • IBM RISCWatch embedded debugger tool
  • Instruction set simulator (ISS) model
  • PowerPC 476-enabled GNU gcc compiler and toolchain


Performance:*      2.5 DMIPS per MHz
Dhrystone 2.1
Technology      IBM CMOS Silicon-on-Insulator (SOI) 45 nm; eight metal layer utilization
Processor clock frequency*      1.6 GHz
Power dissipation (total)*      1.6 W (estimated)
Size*      3.6 mm2
Availability      IBM ASIC Cu-45 hard core

* Preliminary estimates; subject to change

© Copyright International Business Machines Corporation 2008, 2009
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Printed in the United States of America September 2009

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